Along with the recent trend for the miniaturization of electronic products, there has been a demand for multilayer ceramic electronic components to be compact in size, while having high capacitance.
To achieve the above, there have been various attempts made to reduce the thickness of a dielectric layer and an internal electrode, and also for the implementation thereof in multiple layers. In this context, recently, multilayer ceramic electronic components using a thinned dielectric layer and having an increased number of layers have been produced.
In particular, there has been an increasing demand for multilayer ceramic electronic components for high voltage application, to have high withstand voltage properties.
However, such a dielectric layer, when not sufficiently thick, may break down under a relatively low voltage, and thus cannot be utilized for high voltage applications.
Therefore, such a dielectric layer may be designed to have a large thickness for high voltage application, thereby reducing an applied voltage per unit thickness thereof, to be able to withstand high voltages.
Further, to achieve high-voltage reliability of capacitance and high reliability, a thick dielectric layer may be disposed in the center portion of a multilayer ceramic capacitor, so the multilayer ceramic capacitor may have a structure in which a ceramic buffer layer is disposed in the center of repeatedly layered internal electrode layers.
However, a conventional ceramic buffer layer may not be sufficiently effective in improving withstand voltage properties due to its thickness being small. Further, although a ceramic buffer layer having a thickness above a certain level may lead to an increase in withstand voltage properties, when the thickness of such a ceramic buffer layer becomes excessively large, the thickness of an active portion may be reduced as a result, leading to a decrease in withstand voltage properties. Therefore, it is necessary to determine an appropriate thickness range for the ceramic buffer layer.